On-Chip Acceleration

Power 11 Matrix Math Acceleration

The AI acceleration most AS/400 shops already own and have never switched on. It is inside every core of the processor, it costs nothing extra, and it is the cheapest honest answer to a first AI pilot.

Vendor: IBM Availability: Already present in every Power 10 and Power 11 core. Power 11 became generally available on July 25, 2025. Process node: Built into the Power processor Operating environment: Available to partitions on the same physical Power server, subject to the runtime and operating system you choose Deployment: On-chip, no additional hardware

Matrix Math Acceleration is a small piece of specialist circuitry built into every single core of a Power 10 or Power 11 processor. Most chips make you bolt on a separate co-processor to get this. IBM put it in the core.

Here is the plain version. AI models spend most of their time multiplying grids of numbers together. That is genuinely almost all of it. Matrix Math Acceleration is circuitry that does exactly that one operation very quickly. It is like having a calculator built into your pen instead of reaching for one in a drawer.

Why an AS/400 shop should care

Because it is already paid for. If you are on Power 10 or Power 11, this acceleration is sitting in the machine right now, on the same physical server as your production partitions. There is no card to order, no drawer to rack, and no new power circuit to run. For a first pilot, that removes every procurement argument at once.

IBM built the Power S1112, a one-socket Power 11 system announced in July 2026, specifically around this idea: handle inference locally, close to where the data already lives, rather than shipping it out to a cloud service and waiting for the answer to come back.

Where it runs out of road

On-chip acceleration shares the processor with everything else. Your production work and your AI work are drinking from the same cup. A small scoring model checking invoices for anomalies is a reasonable neighbour. A large generative model answering questions all day is not, and that is the point where the Spyre card starts to make sense.

On-chip acceleration does not mean a model runs natively inside IBM i. It means the silicon underneath your partitions can do the maths quickly. You still have to decide which operating system and which runtime the model itself lives in, and verify core, memory, and headroom against IBM's current guidance before sizing anything.