Open Memory Interface (OMI)
OMI is the high-speed link between a Power 11 processor and each memory card, and IBM built it so the processor is not locked to one memory generation. Each OMI channel carries exactly one memory card, so on a Power 11 server the channel count is the memory slot count, and the channel rate of up to 32 Gb/s is what keeps the on-chip AI matrix engines fed.
What is the Open Memory Interface?
It is the wiring between the processor and the memory. On most servers that wiring is a wide, flat bundle of short wires, and every wire has to stay in step with the others. OMI replaces that bundle with a small number of very fast lanes. Picture a toll road. Instead of a hundred narrow lanes that all have to creep forward together, you run eight lanes and move traffic through them quickly. Fewer wires have to cross the connector, so the signal stays clean at a higher speed.
- IBM Redbooks calls OMI a high-speed, low-latency memory interface developed by IBM to decouple memory technology from the processor interface.
- IBM also writes the name as the OpenCAPI Memory Interface. Both names mean the same link.
- OMI is technology-independent. Normal memory wiring is tied to one memory type, such as DDR4 or DDR5. OMI is not, because the smart part sits on the memory card instead of in the processor.
- One OMI channel connects to one 4U DDIMM. DDIMM is differential DIMM, the memory card a Power 11 server takes instead of a plain memory stick. So counting channels counts slots.
- OMI grew out of OpenCAPI, the open standard IBM started for attaching accelerators and memory to Power processors. In August 2022 the OpenCAPI Consortium agreed to hand its specifications to the CXL Consortium, which now hosts the OpenCAPI archive, including its 25 Gbps and 32 Gbps signaling specifications.
Why does OMI matter for AI work?
Because an AI answer is mostly memory traffic. The processor has to pull model weights through itself for every token it produces. The matrix engines on the chip can only work as fast as memory hands data over. If the link is slow, fast engines sit idle. IBM makes this link part of its AI story directly: it says the Power 11 vector units benefit from a 32-channel DDR5 OMI design that delivers the sustained memory throughput those units need for large tensors, streaming datasets and real-time analytics.
OMI also feeds the Spyre Accelerator card, not just the processor. IBM Redbooks publication SG24-8592, first edition March 2026, says the Spyre Accelerator on Power 11 uses its own on-card LPDDR5 memory alongside a Power 11 OMI-based DDR5 subsystem, and that the OMI improvements support the host-side work the card depends on: command dispatch, input and output, preprocessing and postprocessing. Read that as design intent rather than a measured result on your workload, and remember that a faster link does not raise the ceiling on a card that is already busy.
How fast is one OMI channel?
Here is the part that confuses people. One channel carries two different speed numbers, and IBM lists both. The number in MHz or Mbps is the clock on the memory chips. The number in Gb/s is the rate of the OMI link itself. IBM pairs them in its own feature tables: 4000 MHz memory sits on a 32 Gb/s OMI link, and 4800 MHz memory sits on a 38.4 Gb/s link. So when you see 4000 and 32 beside each other, they are not a contradiction. They describe two different parts of the same channel.
OMI link rate for a single memory channel
All three figures come from IBM Redbooks publication SG24-8589, October 2025. The book says the OMI now runs at a maximum of 32 Gbps with DDR5 against 25.6 Gbps on the Power E1050, and a footnote to its memory feature table adds that the DDIMM supports up to 4800 MHz and 38.4 Gb/s OMI while the E1150 system design is limited to 4000 MHz and 32 Gb/s. The gap is a system design choice, not a card limit, so do not buy a card expecting the top number on this machine.
What changed in the memory bus between the Power E1050 and the Power E1150
| Memory bus figure | Power E1050 | Power E1150 |
|---|---|---|
| Data rate per OMI channel | 2666 Mbps or 3200 Mbps | 4000 Mbps |
| OMI link rate per channel | 25.6 Gb/s | 32 Gb/s |
| Bandwidth per processor socket | 409 GB/s | 512 GB/s |
| Maximum system memory | 16 TB | 16 TB |
From the comparison table and the memory bus text in IBM Redbooks publication SG24-8589, October 2025. Both socket bandwidth figures are for a dual-chip module, the two-chip processor package IBM calls a DCM. The capacity ceiling did not move, so this generation bought speed rather than room.
How many OMI channels does a Power 11 server have?
Count the processor packages and you have your answer, because channels come from the processor. A dual-chip module brings 16 channels, 8 from each of its two chips. The smaller entry single-chip module brings fewer, and it also runs a slower channel rate. That is the quiet cost of the cheaper processor option: you lose slots and speed at the same time.
OMI channels and memory slots by Power 11 system
| Power 11 system | Processor packages | OMI channels and DDIMM slots | Data rate per channel |
|---|---|---|---|
| Power S1122 or Power S1124 | Two dual-chip modules | 32 | 4000 or 4800 Mbps |
| Power S1122 or Power S1124 | Two entry single-chip modules | 16 | 4000 Mbps |
| Power E1150, all four sockets filled | Four dual-chip modules | 64 | 4000 Mbps |
Scale-out rows from IBM Redbooks publication SG24-8590, October 2025, which also notes that on an entry single-chip module all the active OMI interfaces sit on chip 0 and none on chip 1. The E1150 row is from SG24-8589, which states that each Power 11 DCM has 16 OMI busses or channels, 8 from each of the two chips, that each channel connects to one 4U DDIMM, and that the E1150 supports up to 64 OMI slots with all four sockets populated, for 16 TB of memory. Exact channel rate depends on the memory feature code you order, so check it against your machine type.
Is a serial memory link reliable enough to trust?
This is the fair question. A long bundle of slow wires fails in obvious ways. A few very fast lanes can be upset by a single bad bit. IBM answers it by building the recovery into the link, and by pointing out that OMI has fewer critical signals crossing the connector than a standard memory design does, which is one less thing to go wrong.
- The link between the memory buffer chip and the processor memory controller is protected by dynamic lane calibration, so it keeps tuning itself while the server runs.
- A CRC retry and recovery facility retransmits lost frames. CRC is a cyclic redundancy check, a short math fingerprint that shows whether the data arrived intact. This lets the channel survive an occasional flipped bit instead of failing.
- If a lane dies outright, the server can cut the channel from 8 lanes down to 4 and keep running. It does this separately for each direction, so a fault on the way in does not cost you the way out.
- IBM lists the Open Memory Interface with differential DIMMs as a reliability feature of the Power E1150, alongside Active Memory Mirroring for the hypervisor and an enterprise-grade service processor.
Being technology-independent has a money side too. IBM says the Power 11 portfolio supports OMI DDR4 memory migrated from Power 10 high-end systems, and that the Power E1150 accepts existing memory from an E1050 it replaces, including DDR4 DDIMMs, as part of a serial number upgrade. IBM gives the reason plainly: protecting a client investment in memory technology. Feature codes still differ between generations, so confirm yours with your reseller and your machine type in hand rather than assuming the cards move.
Related Terms
Differential DIMM (DDIMM)
A DDIMM is the memory card an IBM Power 11 or Power 10 server takes in place of a plain DDR memory stick. It carries its own buffer chip and plugs into an Open Memory Interface slot, which is how a two-socket Power S1124 reaches the 2456 GBps memory bandwidth ceiling IBM lists for feeding data into an AI model.
IBM Power E1150
The Power E1150 is the midrange IBM Power 11 server, machine type 9043-MRU, and IBM lists it for 8, 12, 16 or 24 Spyre AI accelerator cards ... the same card ceiling as the smaller S1124. It is also the one Power 11 model an IBM i shop cannot move production onto, because IBM does not support IBM i on it.
IBM Power S1124
The Power S1124 is the largest scale-out IBM Power 11 server, machine type 9824-42A, and IBM lists it for 8, 12, 16 or 24 Spyre AI accelerator cards ... but only when both processor modules are installed. An IBM i shop can keep production on IBM i 7.4 TR12 or later and run model inference in a Red Hat Enterprise Linux partition on the same 4U machine.
Matrix Math Acceleration (MMA)
An on-chip acceleration feature in IBM Power10 and Power11 processors that speeds up the matrix math operations used in AI inferencing, without requiring a separate GPU.
Spyre Accelerator
IBM's PCIe AI inference card. On IBM Power 11 it carries 32 cores, 128 GB of memory, and more than 300 TOPS inside a 75 watt envelope.