Telum II
IBM's z17 mainframe processor, with an AI accelerator on the chip itself. It does not go in a Power server, but it is where IBM's current AI hardware argument was proven.
Telum II runs eight cores at 5.5 GHz with 360 MB of on-chip cache, an integrated AI accelerator, and an integrated data processing unit for input and output. It was first shown publicly at Hot Chips in August 2024 and ships in IBM z17. Its relevance to an IBM Power buyer is indirect but real: the original Telum proved that scoring a transaction while the transaction is still happening requires the AI engine to sit next to the data rather than on a separate server. That principle produced the AIU, then the Spyre Accelerator, and it is the same principle behind on-chip Matrix Math Acceleration in Power.
Related Terms
Artificial Intelligence Unit
The IBM Research prototype chip that became the commercial Spyre Accelerator. Thirty-two cores, never sold.
Spyre Accelerator
IBM's PCIe AI inference card. On IBM Power 11 it carries 32 cores, 128 GB of memory, and more than 300 TOPS inside a 75 watt envelope.
Matrix Math Acceleration (MMA)
An on-chip acceleration feature in IBM Power10 and Power11 processors that speeds up the matrix math operations used in AI inferencing, without requiring a separate GPU.