From 2 nm to 0.7 nm: How IBM Actually Makes AI Chips

There is a common assumption in AI budgeting that goes roughly like this: the hardware is expensive, the electricity is worse, and both will keep getting worse forever. It is worth knowing that the people who invent transistors disagree, and worth knowing why.

IBM sold its chip manufacturing business years ago. What it kept was the laboratory, and the laboratory is where the industry's current leading transistor design came from. That is an unusual arrangement and it is why IBM keeps appearing in chip news despite not owning a large factory.

The 2 nm milestone, and what a nanosheet is

In May 2021 IBM announced the world's first 2 nanometre chip. The design used a three-layer stack of silicon nanosheets in a gate-all-around arrangement, which is a long way of saying the electrical switch wraps completely around the channel the current flows through rather than sitting on one side of it.

A rough analogy: imagine gripping a rope with one finger pressed against it, versus closing your whole hand around it. The full grip gives far better control. Better control means less leakage, and less leakage means less wasted electricity. IBM's published figures were 45 percent better performance, or 75 percent lower power, compared with a 7 nm chip.

That nanosheet approach is now the leading-edge architecture across the industry. It is the clearest example of what IBM's laboratory actually produces: not chips you buy from IBM, but designs everyone ends up using.

NanoStack, and going up instead of sideways

On June 25, 2026 IBM announced the first transistor below one nanometre: a 0.7 nm node, which the industry also writes as 7 angstroms. The architecture is called NanoStack and it is described as the first known three-dimensional nanosheet design.

The idea is easier than the name. For decades, making chips denser meant making each transistor smaller and laying more of them out side by side on a flat surface. NanoStack stacks them vertically and staggers them instead, the way a car park adds floors rather than buying more land. Each stacked layer can also use a different combination of materials, so one layer can be tuned for speed while another is tuned for low power.

The headline number is nearly 100 billion transistors on a chip the size of a fingernail, roughly twice the density of the 2 nm chip from 2021. IBM says production is possible as early as the next five years, which anyone who has watched this industry will correctly read as do not plan around it.

Where the work happens, and who else is in the room

All of this comes out of the Albany NanoTech Complex in upstate New York. IBM names Lam Research, Tokyo Electron, SCREEN Semiconductor Solutions, and ASML as partners on the NanoStack work. In March 2026 IBM and Lam Research separately announced a collaboration specifically on sub-1 nm logic scaling.

New York State, IBM, Micron and other industry partners also committed to a 10 billion dollar expansion of the Albany complex, including a High NA EUV centre. High NA EUV is the next generation of the machinery that prints patterns onto silicon, and it is the practical bottleneck between a laboratory transistor and a manufacturable one.

The Japan connection

There is a second part of this story that gets less attention. Rapidus, a Japanese manufacturer, sent more than 150 engineers to Albany across 2023 and 2024 to learn IBM's 2 nm process. Around 80 of them have since returned to Chitose in Hokkaido to tune the process for production.

Rapidus started a pilot line at its Chitose foundry in April 2025, produced working 2 nm prototypes with IBM and imec during 2025, and is targeting mass production in 2027. This is how IBM's laboratory work reaches actual silicon without IBM owning the factory.

Why an AS/400 shop should care, and how much

Care a little, and only in the right conversation. Nothing here changes what you can order for a Power 11 server this year. The Spyre Accelerator is built on a 5 nm process. NanoStack is three generations beyond it and five years away at best.

What it is genuinely useful for is answering the board-level question. When somebody asks whether investing in AI infrastructure now means being stuck with expensive, power-hungry hardware forever, the honest answer is that the people inventing the transistors are working hard in the other direction, with named partners, a funded laboratory, and results published on a regular cadence.

That is not a reason to delay a project. Waiting for better silicon is a loop with no exit. It is a reason to be confident that the current generation is a starting point rather than a ceiling.