Glossary
Nanosheet transistor
The gate-all-around transistor design IBM demonstrated at 2 nm in 2021, now the industry's leading-edge architecture.
A nanosheet transistor uses stacked sheets of silicon with the electrical gate wrapping completely around the channel the current flows through, rather than sitting on one side of it. The full wrap gives much better control over the current, which means less leakage and less wasted power. IBM announced the world's first 2 nm chip using a three-layer nanosheet gate-all-around structure in May 2021, reporting 45 percent better performance or 75 percent lower power consumption than a 7 nm chip. The design is now used across the industry at the leading edge, and IBM's NanoStack work extends it into three dimensions.