NanoStack
IBM's 0.7 nm transistor architecture, announced June 25, 2026. The first published transistor below one nanometre.
NanoStack is described by IBM as the first known three-dimensional nanosheet transistor architecture. Rather than shrinking transistors and laying them out side by side, it stacks and staggers them vertically using 3D sequential integration, and allows different material combinations in each stacked layer. IBM reports nearly 100 billion transistors on a chip the size of a fingernail, roughly twice the density of its 2021 2 nm chip, with up to 50 percent more performance or 70 percent greater energy efficiency than the 2 nm node. The work is done at the Albany NanoTech Complex with Lam Research, Tokyo Electron, SCREEN Semiconductor Solutions, and ASML. IBM says production is possible as early as the next five years.
Related Terms
Nanosheet transistor
The gate-all-around transistor design IBM demonstrated at 2 nm in 2021, now the industry's leading-edge architecture.
NorthPole
An IBM Research chip with no off-chip memory at all, claiming 25 times the energy efficiency of a conventional architecture. Research only, not for sale.
Spyre Accelerator
IBM's PCIe AI inference card. On IBM Power 11 it carries 32 cores, 128 GB of memory, and more than 300 TOPS inside a 75 watt envelope.