IBM Opened the Spyre Card, and the Design Explains the Product
IBM has finally shown enough of the Spyre Accelerator to explain why the card looks modest beside a giant training GPU. It is not trying to win the same job. Spyre is built to answer from trained models at steady production load, close to enterprise data, inside a strict power budget.
That is useful before a purchase because it separates a real inference card from a vague promise that any AI work will run faster. If the job is training, this is the wrong card. If the job is serving supported models with predictable latency, the design starts to make sense.
The card IBM Research described
| Design fact | Published detail | Why it matters |
|---|---|---|
| Accelerator cores | 32 | The work is spread across many inference-focused cores |
| Chip process | 5 nm | A modern process helps the card stay compact and efficient |
| Transistors | 25.6 billion | This is a full inference processor, not a small coprocessor |
| Card power | 75 watts | Power and cooling are part of the product's enterprise fit |
Published IBM specifications describe the chip and card. Real workload speed still depends on the model, precision, batch, runtime, and complete Power configuration.
The memory is part of the answer
Spyre places dedicated memory around the processor and gives its cores local working space. That reduces the time and electricity spent moving model data back and forth. IBM's dataflow design keeps useful work moving through the chip instead of making every step wait on a distant shared resource.
The card also has its own power-control loops. IBM Research describes them as a way to hold performance steady inside the card's power limit instead of treating power as an afterthought. That matters in a Power server where one accelerator has to live beside processors, memory, storage adapters, and everything else the machine already does.
Why IBM chose inference
Training creates a model. Inference uses that trained model to answer. Most business systems spend their lives answering, so IBM designed Spyre for the second job. Continuous batching in the supported runtime lets the card keep several requests moving instead of waiting for one request at a time.
That fits the IBM i world better than a training-first story. The useful question is not how quickly the shop can create a giant model. It is whether a supported model can answer beside Db2 for i data without sending the business record across the internet.
The hardware tells the truth about the product: Spyre is a serving accelerator. Judge it with the model, batch, latency, and runtime you will actually operate, not with a training benchmark from a different class of machine.
Sources
- IBM Research: Lifting the cover on the IBM Spyre Accelerator
- IBM Research: Building the IBM Spyre Accelerator
- IBM Research Spyre technical paper
- IBM Spyre Accelerator for Power documentation
Related Tools & Vendors
IBM Spyre Accelerator for Power
A 75 watt PCIe card that adds more than 300 TOPS of AI inference to a Power 11 server. It is the only IBM AI chip an AS/400 shop can actually order as an add-on, and it comes with a short list of things it refuses to work without.
IBM Artificial Intelligence Unit (AIU)
The research chip that became the card you can order. The AIU is why the Spyre Accelerator has 32 cores and why those cores look so much like the AI engine already inside an IBM Z processor.
IBM NorthPole
A research chip with no separate memory at all. NorthPole claims 25 times the energy efficiency of a conventional design by refusing to move data, and IBM has already run a Granite model on it.
vLLM
The open source engine inside the product IBM requires for a Spyre card. Worth knowing by name, because it is the reason the same card can answer many people at once instead of queuing them.